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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA 68030/040 PECL-TTL Clock Driver The MC10H/100H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its superior skew characteristic. The H640 includes divide-by-two and divide-by-four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol). The 10H version is compatible with MECL 10HTM ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V). MC10H640 MC100H640 68030/040 PECL-TTL CLOCK DRIVER * * * * * * Generates Clocks for 68030/040 Meets 030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and PECL Power/Ground Pins Asynchronous Reset Single +5.0V Supply FN SUFFIX PLASTIC PACKAGE CASE 776-02 Function Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH. Power-Up: The device is designed to have the POS edges of the /2 and /4 outputs synchronized at power up. Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this case, the DE side of the input is pulled LOW, and DE goes HIGH. VT 25 Q2 GT GT Q3 VT VT Q0 26 27 28 1 2 3 4 5 Q1 6 GT 7 GT 8 Q4 9 Q5 10 VT 11 SEL VT 24 Q1 23 GT 22 GT 21 Q0 20 VT 19 18 17 16 VBB DE DE VE R GE DT Pinout: 28-Lead PLCC (Top View) 15 14 13 12 11/93 (c) Motorola, Inc. 1996 2-1 REV 3 MC10H640 MC100H640 LOGIC DIAGRAM TTL Outputs Q0 PIN NAMES PIN GT VT VE GE DE, DE VBB DT Qn, Qn SEL R FUNCTION TTL Ground (0 V) TTL VCC (+5.0 V) ECL VCC (+5.0 V) ECL Ground (0 V) ECL Signal Input (positive ECL) VBB Reference Output TTL Signal Input Signal Outputs (TTL) Input Select (TTL) Reset (TTL) Q1 TTL/ECL Clock Inputs VBB DE DE DT MUX /2 Q2 Q3 Q0 Q1 SEL /4 Q4 Q5 TTL Control Inputs R AC CHARACTERISTICS (VT = VE = 5.0V 5%) 0C Symbol tPLH tPLH tskwd* tPLH tPLH tPLH tPLH tPD tR tF fmax tpw trr Characteristic Propagation Delay ECL D to Output Propagation Delay TTL D to Output Within-Device Skew Propagation Delay ECL D to Output Propagation Delay TTL D to Output Propagation Delay ECL D to Output Propagation Delay TTL D to Output Propagation Delay R to Output Output Rise/Fall Time 0.8 V - 2.0 V Maximum Input Frequency Minimum Pulse Width Reset Recovery Time All Outputs All Outputs 135 1.50 1.25 Q4, Q5 Q0, Q1 4.9 5.0 4.9 5.0 4.3 Q0-Q3 Min 4.9 5.0 Max 5.9 6.0 0.5 5.9 6.0 5.9 6.0 6.3 2.5 2.5 135 1.50 1.25 4.9 5.0 4.9 5.0 4.3 Min 4.9 5.0 25C Max 5.9 6.0 0.5 5.9 6.0 5.9 6.0 6.3 2.5 2.5 135 1.50 1.25 5.2 5.3 5.2 5.3 5.0 Min 5.2 5.3 85C Max 6.2 6.3 0.5 6.2 6.3 6.2 6.3 7.0 2.5 2.5 Unit ns ns ns ns ns ns ns ns ns MHz ns ns Condition CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF * Within-Device Skew defined as identical transitions on similar paths through a device. MOTOROLA 2-2 MECL Data DL122 -- Rev 6 MC10H640 MC100H640 VCC and CLOAD RANGES TO MEET DUTY CYCLE REQUIREMENTS (0C TA 85C Output Duty Cycle Measured Relative to 1.5V) Symbol Characteristic Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 11.5 ns at fout 40 MHz Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 9.5 ns at 40 < fout 50 MHz VCC CL VCC CL Min 4.75 10 4.875 15 Nom 5.0 5.0 Max 5.25 50 5.125 27 Unit V pF V pF Condition Q0-Q3 Q0-Q1 Q0-Q3 DC CHARACTERISTICS (VT = VE = 5.0 V 5%) 0C Symbol IEE ICCH ICCL Characteristic Power Supply Current ECL TTL Min Max 57 30 30 Min 25C Max 57 30 30 Min 85C Max 57 30 30 Unit mA mA mA Condition VE Pin Total all VT pins TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%) 0C Symbol VIH VIL IIH IIL VOH VOL VIK IOS Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Output Short Circuit Current -100 2.5 2.0 0.5 -1.2 -225 -100 Min 2.0 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 -100 Max Min 2.0 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 25C Max Min 2.0 0.8 20 100 -0.6 A mA V V V mA VIN = 2.7V VIN = 7.0V VIN = 0.5V IOH = -3.0mA IOH = -15mA IOL = 24mA IIN = -18mA VOUT = 0V 85C Max Unit V Condition MECL Data DL122 -- Rev 6 2-3 MOTOROLA MC10H640 MC100H640 10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V 5%) 0C Symbol IIH IIL VIH* VIL* VBB* Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage Min 0.5 3.83 3.05 3.62 4.16 3.52 3.73 Max 225 0.5 3.87 3.05 3.65 4.19 3.52 3.75 Min 25C Max 175 0.5 3.94 3.05 3.69 4.28 3.555 3.81 V V VE = 5.0V Min 85C Max 175 Unit A Condition *NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V. 100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V 5%) 0C Symbol IIH IIL VIH* VIL* Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Min 0.5 3.835 3.19 4.12 3.525 Max 225 0.5 3.835 3.19 4.12 3.525 Min 25C Max 175 0.5 3.835 3.19 4.12 3.525 V VE = 5.0V Min 85C Max 175 Unit A Condition VBB* Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V *NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V. 10/100H640 DUTY CYCLE CONTROL To maintain a duty cycle of 5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2. For a 2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up. Best duty cycle control is obtained with a single P load and minimum line length. MOTOROLA 2-4 MECL Data DL122 -- Rev 6 MC10H640 MC100H640 11 5.25 VCC 5 VCC 4.75 VCC PW (ns) 10 NEGATIVE PULSE WIDTH (ns) 11 10 4.75 VCC 5 VCC 9 5.25 VCC 9 0 25 50 LOAD (pF) 75 85 0 25 50 LOAD (pF) 75 85 Figure 1. Positive Pulse Width at 25C Ambient and 50 MHz Out Figure 2. Negative Pulse Width @ 50 MHz Out and 25C Ambient 11 NEGATIVE PULSE WIDTH (ns) 5.125 VCC 5 VCC 4.875 VCC 10 11 POSITIVE PULSE WIDTH (ns) 10 4.875 VCC 5 VCC 5.125 VCC 9 9 0 25 50 LOAD (pF) 75 85 0 25 50 LOAD (pF) 75 85 Figure 3. Positive Pulse Width at 25C Ambient at 50 MHz Out Figure 4. Negative Pulse Width @ 50 MHz Out and 25C Ambient 11 NEGATIVE PULSE WIDTH (ns) 50 pF 25 pF 10 11 10 pF POSITIVE PULSE WIDTH (ns) 10 25 pF 10 pF 9 9 0 25 50 TEMPERATURE (C) 75 85 0 25 50 TEMPERATURE (C) 75 85 Figure 5. Temperature versus Positive Pulse Width for 100H640 at 50 MHz and +5.0 V VCC Figure 6. Temperature versus Negative Pulse Width for MC100H640 @ 50 MHz and +5.0 V VCC MECL Data DL122 -- Rev 6 2-5 MOTOROLA MC10H640 MC100H640 6.2 4.75 V 6.0 5V 5.25 V TPD++ (ns) 5.8 5.6 5.4 5.2 0 25 50 CLOAD (pF) 75 85 Figure 7. TP versus Load Typical at TA = 25C DT RESET, R Rtrec Rtpw Q0, Q1, Q2, Q3 Q0, Q1 Q4, Q5 Figure 8. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset Pulse Din Q0 Q1 Q3 Q2 Q4 & Q5 AFTER POWER UP OUTPUTS Q4 & Q5 WILL SYN WITH POSITIVE EDGES OF Din & Q0 Q3 & NEGATIVE EDGES OF Q0 & Q1 Figure 9. Output Timing Diagram MOTOROLA 2-6 MECL Data DL122 -- Rev 6 MC10H640 MC100H640 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D B -N- Y BRK U D Z -L- -M- 0.007 (0.180) M 0.007 (0.180) M T L-M S N S S T L-M N S W 28 1 D X VIEW D-D G1 0.010 (0.250) S T L-M S N S V A Z R C 0.007 (0.180) 0.007 (0.180) M T L-M T L-M S N N S H 0.007 (0.180) M T L-M S N S M S S E 0.004 (0.100) G G1 0.010 (0.250) S K1 J -T- VIEW S SEATING PLANE K F VIEW S 0.007 (0.180) M T L-M S N S T L-M S N S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 --- MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 --- MECL Data DL122 -- Rev 6 2-7 MOTOROLA MC10H640 MC100H640 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA 2-8 *MC10H640/D* MC10H640/D MECL Data DL122 -- Rev 6 |
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